1. Field of the invention
The present invention relates generally to switching converters.
2. Description of the Related Art
Switched-mode power supplies (SMPS's) provide superior voltage conversion efficiency because they regulate an output voltage with transistor switches that are either on or off so that they never operate in the linear region in which both current and voltage are nonzero. Because at least one of transistor current and voltage is therefore always close to zero, dissipation is greatly reduced.
Because of their high efficiencies, SMPS's have been found to be particularly useful in a variety of portable devices (e.g., mobile phones, digital cameras, digital radios, portable disk drives and media players) that are powered by internal batteries (e.g., lithium batteries). Although other parameters are also important in these devices, operating efficiency is especially critical as it directly affects battery life. Typical high-efficiency SMPS's (e.g., step-down buck switching converters) are configured with an arrangement of an inductor, input and output capacitors, and control and synchronous switches. They may be provided in extremely small (e.g., 1.3×0.9×0.6 mm) configurations (e.g., chip scale packages).
Power losses in these configurations include conduction losses and switching losses. Conduction losses occur as switched currents pass through the inductor and capacitor and associated interconnecting traces. These losses can be limited by designing these components (e.g., with ceramic inductors and capacitors) to reduce parameters such as winding loss, core loss, dielectric loss and capacitor leakage. Another important contributor to the conduction losses is generated during each SMPS duty cycle as switch currents flow through the on-resistances of the switches which are typically realized with metal-oxide-semiconductor field effect transistors (MOSFET's). The control and synchronous transistors also contribute to the switching losses because they pass currents between sources and drains during finite transition periods in which they turn on and turn off. As SMPS's operate at higher clock rates, the switching losses become more important because the switching periods of the transistors reduces but the transition periods remain constant.
SMPS's are often designed to operate in a pulse-width modulation (PWM) mode in which the duty cycle of the control and synchronous transistors is varied to thereby control the SMPS output voltage. When operated with heavy loads (i.e., high output currents), well-designed SMPS obtain high efficiencies (e.g., greater than 90%) in the PWM mode. However, as the load reduces (i.e., output current decreases) the PWM mode efficiency rapidly drops because output conduction and switching losses remain constant as output power drops. Accordingly, SMPS's are often configured to include a pulse-frequency modulation (PFM) mode which is sometimes referred to as a pulse skipping mode. In this mode, conduction pulses have a constant width and are provided (e.g., singly or in bursts) as needed to maintain the output voltage within a voltage window. Although pulse skipping can maintain high efficiencies over a wide range of light loads, it typically fails to match the performance of the PWM mode (e.g., minimal output-voltage ripple and minimal frequency spurs).